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• 3. Generation FISC
— Projects: History, 3. Generation FISC —
FISC: a computer system built around a Z80 CPU.
After the SBCS there came the FISC: flexible instruction set computer. I have no idea, how I came to this name. Like the SBCS, it was built around a Zilog Z80 4 MHz CPU. The system expanded into a second tray stacked on the first. The main board at the back of the tray disapeared.
From left to right:
The card consists of some 30 ICs and features a Z80 CPU, 2 KB EPROM with the operating system, extensible to 8 KB, and two banks with 64 KB each. This was the first real computer I built: it had a reset button!
However, the idea behind the inclusion of the reset push button was another: the system starts up from the operating system in the EPROM. New operating systems can be downloaded from another computer in loaded in RAM. By selecting another memory bank at the front panel thumbwheel switch, the system can re-boot on the downloaded system. Its first run-date was 5. June 1988.
FISC-MC-SPI Interface Card
The main computer to slave processor interface is a 8-bit parallel interface with a 5-bit hardware handshaking. I got the general idea from the IEEE-488 interface, but made it a lot simpler, mainly because I did not know exactly how HP-IB / IEEE-488 worked. It was tested with 22 KBps over 12 meters (36 ft).
Connection to the other computer was made by a 50-pin Amphenol type connector and a complicated cable. The «other» computer was an Osborne Executive portable computer with a 7 inch amber display, also running on a Z80 CPU under CP/M Plus. It had a true IEEE-488 interface that I abused for my purposes by software control.
The smaller connector on the front panel connected to a small display unit with 5 LEDs that showed the status of the 5 handshake lines.
Great plans we had, my colleague and I, when we mail-ordered two 4-track cassette recordes from the UK. We wanted to make that sloppy ZX cassette interface faster and thought about recording nibbles (4 bits) instead of just one bit at a time. Besides, recording tone codes was definitly old fashened when diskettes were recorded with the non-return to zero (NRZ) method. My colleague did most of the hardware development.
The theory was ok, the electronics clever, the cassettes unusable. I experimented on the 4-track open reel tape machine with 38 cm/s (15 inch per second) speed. The results were much better but still unusable.
The problem was a purely mechanical one. The tracks may appear synchronized when listening to canned sound, investigating pulses with an oscilloscope reveals, that this is not true at all. The oscilloscope trace synchronized by the signal of track one is rock steady, the second one from track 2, 3 or 4 moves randomly foreward and backward.
This was a great disappointment but nevertheless a very enlightning experience. It became quite clear why streamer tapes have a heavy metallic plate as support. Without such a sturdy support, the tape will never be guided stable enough in front of the recording and playback head.
The Z80 assembly source code and the assembled EPROM code is available here as fisc20h.zip (14 KB).
Electrically Programmable Read Only Memory were the means for non-volatile memory. In the 1980s, 2048 x 8 bit EPEROMs (2716 = 16 Kb) organized as 2 KB devices were cheap and cost about as much as a bottle of quality wine. They could be erased by leaving them for about 3 weeks under direct sunlight (cheapest means) or glued to a fluorescent tube for a few days (quite cheap) or subject them to ultraviolett light for 10 minutes or so (expensive).
To programm them, a burner was needed with a price tag that would buy you a nice laptop today. Understanding how long to put 25 V on the programming pin and a bit of software was all that was needed to burn them, though.
If you ever manually coded 2 KB memory, you know that that much of storage capacity is almost infinite. Besides, 4 KB EPROMs were just not affordable. With the Extended BASIC project finally working, I needed a means to burn the code into an EPROM. Using the programming device at the workplace seemed a bit too easy — the way is the goal.
On the left of the board is the 5 V / 25 V PS (power supply) mounted on a separate breadboard. It accepts 220 V from the AC mains. To the right the latches, control and SBCS bus interface.
The functional block diagram of this unit that cost me about 2% to build than the price tag of an EPROMer on the market at that time, is shown below. The most expensive part was the ZIP (zero insertion pressure) socket on the front panel.
If I remember correctly, 25 V had to be put on the programming pin for 50 ms, programming a 2 KB EPROM took almost 2 minutes. Later, larger EPROMs of e.g. 32 KB (27256) used another burning scheme and 12.5 V. The programming pin was set to the programming voltage for a few milliseconds only and with a read-after-write checked, whether the cell took the programming. If not, it was tried again with a slightly longer burntime. The time saving was considerable.
The Z80 assembly source code and the assembled EPROM code is available here as epromer.zip (25 KB). This includes also a fig-FORTH-79 source file and the turnkey run-module for CP/M 3.0.
FISC-CVGSEQ Sequencer Card
On 4. June 1989 the control voltage generator sequencer worked. I have had an analog voltage controlled electronic music synthesizer (VCEMS) for quite some time and played around with it. I never had any musical training and concentrated on other things like creating sound sculptures. When I wanted to play a tune, I exercised for a couple of weeks or programmed the analog sequencer with two banks of 12 potmeters.
The analog sequencer was too limitted, as I was with my awkward fingers. Since the VCEMS used linear voltages and its VCO had a logarithmizer built in to produce the twelvth root of two increments between the half tones, assembling a computerized sequencer seemd a simple task to me.
I constructed it around a 8255 peripheral interface. For the digital to analog converter I used CMOS 4051 8 to 3 multiplexers. With 3 bits, I opened a shorter or longer path in a eight 100 ohms resistor ladder tied to a reference voltage of 1 V. With two multiplexers and resistor ladders, I could produce 16 halftones to the octave. If I tuned it correctly and used only 12, I had an even tempered scale. With a third multiplexer I created the octaves in the same manner. In total, I got to twice 7½ octaves.
The voltages produced were mixed with a LM348 (741-type) operational amplifier and buffered. I made two banks since my VCEMS system has 2 VCOs. The musical output was recorded on a 4 track tape deck. The problem of synchronizing the tracks remained.
I added an AF transformer and three CMOS inverters in a 4069 package operating the first two in a final loop configuration (1:10) as high gain, high impedance amplifiers and the third in an infinite loop. Finally, I got a logic level from a 300 mV audio signal that could be read by the 8255.
I recorded a test tone on one track of the tape machine, and played it back. The software listened for it and when it ended (port bit zero again), it started the musical sequence. Thus, the tracks were always in sync.
The Z80 assembly source code and the assembled EPROM code are available here as cvgseq.zip (19 KB). This includes also a compiler-BASIC source file and the turnkey run-module for CP/M 3.0. This program is needed to compile the music synthesizer data (script). The Two-part Invention in F-major by J. S. Bach is included as data script and in loadable compiled form.
FISC-PPS Speech Synthesizer Card
«BYTE» magazine, September 1981, featured an article written by Steven A. Giarcia titled Build an Unlimitted-Vocabulary Speech Synthesizer. Another article by Gerd Zeising Phonem-Assembler für Sprach-Synthese IC SC-01 appeared in the German computer magazin «c't» in 1984. Both articles centered the synthesizer around the SC-01 chip by Vortex. On the 12. December 1987 my speech synthesizer finally worked.
The German article was a software project only, the one in BYTE was also a hardware one. But the idea was to buy the final product for a TRS-80, an Apple II or a Commodore C64 microcomputer. That is why I had to build it myself. The SC-01 was quite expensive, but it was forgiving: I fried it with 15 V instead of 5 V and smoke emanated from it once before I could switch of the power. However, it still worked afterwards.
To interface the SC-01 to the FISC, 6 CMOS ICs were used and two TTL ones. The output was fed to an LM301 operational amplifier. The challenge really was to make the thing also speak German.
On the Osborne Executive computer, I developped a phoneme compiler for the languages German, French and English. I used a compiler BASIC I got with the purchase of the computer and which was more powerful than the Microsoft BASIC interpreter with its line numbers (MSBASIC V.5.1).
I could write sentenses on the Osborne, send them over the bent IEEE-488 port 12 meters to the next room through the Interface card to the speech synthesizer. Its output was fed to an audio mixer that added some reverberation, amplify the signal and send it back to the loudspeakers in front of me.
I was extremly exited about it, but never really did anything that came to something useful with it. After everything worked, I somewhat lost interest in speech synthesis. Pitty, though…
The Z80 assembly source code is available here as scpps.zip (17 KB). This includes also a compiler-BASIC source file of the Phoneme Speech Synthesizer and phoneme lists for the languages English, French and German.
© 2004 - 2018 by Horo Wernli.